;*********************************************************************
;* Title: code-mmmpi-v00.asm
;*********************************************************************
;* Author: R. Allen Murphey
;*
;* License: Copyright (c) 2020-2022 R. Allen Murphey. All Rights Reserved.
;*
;* Description: MEGA-MINI MULTI-PAK INTERFACE (MMMPI)
;*
;* Documentation: MEGAmini Manual
;*   Yamaha YM3526 OPL Datasheet
;*   Yamaha YM3812 OPLII Datasheet and Application Manual
;*   Yamaha YMF262 OPL3 Datasheet
;*   Yamaha YMF278B OPL4 Application Manual
;*   SC16550B Datasheet
;*
;* Include Files: Requires PIA0, PIA1, MPI equates
;*
;* Assembler: lwasm 1.4.2
;*
;* Revision History:
;* Rev #     Date      Who     Comments
;* -----  -----------  ------  ---------------------------------------
;* 00     2020-2021    RAM     Created initial file
;*********************************************************************

                              ; MEGA MINI MPI VIRTUAL SLOT 5 OPL3
MPIOPL30:   equ   $FF50       ; OPL3 REGISTER ARRAY 0 SELECT 01-F5
MPIOPL31:   equ   $FF51       ; OPL3 REGISTER ARRAY 0 DATA - SEE OPL3 EQUATES
MPIOPL32:   equ   $FF52       ; OPL3 REGISTER ARRAY 1 SELECT 01-F5
MPIOPL33:   equ   $FF53       ; OPL3 REGISTER ARRAY 1 DATA - SEE OPL3 EQUATES
MPIOPL34:   equ   $FF54       ; OPL3 RESET

                              ; MEGA MINI MPI VIRTUAL SLOT 6 UARTS
MPIUARTA0:  equ   $FF40       ; UART A TRANSMIT HOLDING REGISTER (THR) / RECEIVE HOLDING REGISTER (RHR)
MPIUARTA1:  equ   $FF41       ; UART A INTERRUPT ENABLE REGISTER (IER)
MPIUARTA2:  equ   $FF42       ; UART A FIFO CONTROL REGISTER (FCR) / INTERRUPT STATUS REGISTER (ISR)
MPIUARTA3:  equ   $FF43       ; UART A LINE CONTROL REGISTER (LCR)
MPIUARTA4:  equ   $FF44       ; UART A MODEM CONTROL REGISTER (MCR)
MPIUARTA5:  equ   $FF45       ; UART A LINE STATUS REGISTER (LSR)
MPIUARTA6:  equ   $FF46       ; UART A MODEM STATUS REGISTER (MSR)
MPIUARTA7:  equ   $FF47       ; UART A SCRATCHPAD REGISTER (SPR)
MPIUARTA8:  equ   $FF48       ; UART A RESET
MPIUARTAA:  equ   $FF4A       ; UART A SECONDARY DATA PORT 16-BIT MSB
MPIUARTAB:  equ   $FF4B       ; UART A SECONDARY DATA PORT 16-BIT LSB

MPIUARTB0:  equ   $FF50       ; UART B TRANSMIT HOLDING REGISTER (THR) / RECEIVE HOLDING REGISTER (RHR)
MPIUARTB1:  equ   $FF51       ; UART B INTERRUPT ENABLE REGISTER (IER)
MPIUARTB2:  equ   $FF52       ; UART B FIFO CONTROL REGISTER (FCR) / INTERRUPT STATUS REGISTER (ISR)
MPIUARTB3:  equ   $FF53       ; UART B LINE CONTROL REGISTER (LCR)
MPIUARTB4:  equ   $FF54       ; UART B MODEM CONTROL REGISTER (MCR)
MPIUARTB5:  equ   $FF55       ; UART B LINE STATUS REGISTER (LSR)
MPIUARTB6:  equ   $FF56       ; UART B MODEM STATUS REGISTER (MSR)
MPIUARTB7:  equ   $FF57       ; UART B SCRATCHPAD REGISTER (SPR)
MPIUARTB8:  equ   $FF58       ; UART B RESET
MPIUARTBA:  equ   $FF5A       ; UART B SECONDARY DATA PORT 16-BIT MSB
MPIUARTBB:  equ   $FF5B       ; UART B SECONDARY DATA PORT 16-BIT LSB

                              ; MEGA MINI MPI VIRTUAL SLOT 16 EXTENDED MPI FEATURES
MPIEXT0:    equ   $FF40       ; IRQ CONTROL REGISTER
MPIEXT1:    equ   $FF41       ; ACTIVE IRQS
MPIEXT2:    equ   $FF42       ; EXTENDED FEATURES REGISTER
MPIEXT3:    equ   $FF43       ; TIMER MSB
MPIEXT4:    equ   $FF44       ; TIMER LSB
MPIEXT5:    equ   $FF45       ; TIMER RESET

                              ; MPISELECT $FF7F CTS3|CTS2|CTS1|CTS0|SCS3|SCS2|SCS1|SCS0

MMMPI:
            rts

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;* End of code-mmmpi-v00.asm
;*********************************************************************