;*********************************************************************
;* Title: code-symphony12-v00.asm
;*********************************************************************
;* Author: R. Allen Murphey
;*
;* License: Copyright (c) 2020-2022 R. Allen Murphey. All Rights Reserved.
;*
;* Description: SYMPHONY-12 4 X PSG DRIVER
;*
;* Documentation: MC6821 PIA Datasheet
;*   General Instruments AY-3-8910/8912 SSG Data Manual Feb 1979
;*
;* Include Files: Requires PIA0, PIA1, MPI, and PSG equates
;*
;* Assembler: lwasm 1.4.2
;*
;* Revision History:
;* Rev #     Date      Who     Comments
;* -----  -----------  ------  ---------------------------------------
;* 00     2020-2021    RAM     Created initial file
;*********************************************************************

S12PORT0:   equ   $FF60       ; SYMPHONY 12 DATA PORT A / DATA DIRECTION A
                              ;       Bit 7 PSG 1-4 8912 pin 21 Data/Address DA7
                              ;       Bit 6 PSG 1-4 8912 pin 22 Data/Address DA6
                              ;       Bit 5 PSG 1-4 8912 pin 23 Data/Address DA5
                              ;       Bit 4 PSG 1-4 8912 pin 24 Data/Address DA4
                              ;       Bit 3 PSG 1-4 8912 pin 25 Data/Address DA3
                              ;       Bit 2 PSG 1-4 8912 pin 26 Data/Address DA2
                              ;       Bit 1 PSG 1-4 8912 pin 27 Data/Address DA1
                              ;       Bit 0 PSG 1-4 8912 pin 28 Data/Address DA0

S12PORT1:   equ   $FF61       ; SYMPHONY 12 CONTROL A
                              ;       Bit 7
                              ;       Bit 6
                              ;       Bit 5
                              ;       Bit 4
                              ;       Bit 3
                              ;       Bit 2 0=FF60 is Data Direction 1=FF60 is Port A
                              ;       Bit 1
                              ;       Bit 0

S12PORT2:   equ   $FF62       ; SYMPHONY 12 DATA PORT B / DATA DIRECTION B
                              ;       Bit 7 PSG D/4 8912 pin 18 Bus Direction BDIR Strobe
                              ;       Bit 6 PSG D/4 8912 pin 20 Bus Control 1 BC1 Strobe
                              ;       Bit 5 PSG C/3 8912 pin 18 Bus Direction BDIR Strobe
                              ;       Bit 4 PSG C/3 8912 pin 20 Bus Control 1 BC1 Strobe
                              ;       Bit 3 PSG B/2 8912 pin 18 Bus Direction BDIR Strobe
                              ;       Bit 2 PSG B/2 8912 pin 20 Bus Control 1 BC1 Strobe
                              ;       Bit 1 PSG A/1 8912 pin 18 Bus Direction BDIR Strobe
                              ;       Bit 0 PSG A/1 8912 pin 20 Bus Control 1 BC1 Strobe
                              ;       BDIR BC2 BC1 PSG Function
                              ;          0   1   0 INACTIVE
                              ;          0   1   1 READ FROM PSG
                              ;          1   1   0 WRITE TO PSG
                              ;          1   1   1 LATCH ADDRESS
                              ;       PSG 1 INACTIVE xxxxxx00
                              ;       PSG 1 READ     xxxxxx01
                              ;       PSG 1 WRITE    xxxxxx10
                              ;       PSG 1 LATCH    xxxxxx11
                              ;       PSG 2 INACTIVE xxxx00xx
                              ;       PSG 2 READ     xxxx01xx
                              ;       PSG 2 WRITE    xxxx10xx
                              ;       PSG 2 LATCH    xxxx11xx
                              ;       PSG 3 INACTIVE xx00xxxx
                              ;       PSG 3 READ     xx01xxxx
                              ;       PSG 3 WRITE    xx10xxxx
                              ;       PSG 3 LATCH    xx11xxxx
                              ;       PSG 4 INACTIVE 00xxxxxx 
                              ;       PSG 4 READ     01xxxxxx
                              ;       PSG 4 WRITE    10xxxxxx
                              ;       PSG 4 LATCH    11xxxxxx

S12PORT3:   equ   $FF63       ; SYMPHONY 12 CONTROL B
                              ;       Bit 7
                              ;       Bit 6
                              ;       Bit 5
                              ;       Bit 4
                              ;       Bit 3
                              ;       Bit 2 0=FF62 is Data Direction 1=FF62 is Port B
                              ;       Bit 1
                              ;       Bit 0

;*********************************************************************
;* RoutineName - expanded name or phrase describing purpose
;*  Brief description
;*
;* I/O: what is expected and produced
;*
;* Calling Convention: how is this called?
;*
;* Returns:
;*
;* Stack Usage: (when needed) structure of stacked data
;*
;* Calls: Info about routines called
;*
;* Changes: registers destroyed.
;*********************************************************************

SYMPHONY12:
            rts

;*********************************************************************
;* Title: code-symphony12-v00.asm
;*********************************************************************