====== Memory Latch Select 256b ======

^ Address Range  ^ Usage  ^
| 0000-7FFF  | Lower 32K RAM  |
| 8000-DFFF  | Upper 32K RAM (24K directly usable)  |
| E000-EFFF  | I/O Address Range  |
| F000-FFEF  | EEPROM  |
| FFF0-FFFF  | MPU Vectors  |

===== The Paging Latch =====

^ ^ ^^^ ^^^^
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Status LED| EEPROM 4K Page ||| RAM 64K Map ||||
| 1 = off, 0 = on | 0-7 ||| 0-15  ||||

===== Status LED =====

Bit 7 controls the "stat" LED

If you store in a $80 it should change the status LED

To be more specific, $80 turns the LED off and $00 turns it on as it is a pulldown and should be on at reset.

===== EEPROM 4K Page Select =====

Bits 6-4 of the Memory Latch Select switches between 4K ROM banks 0 to 7 of the 32K EEPROM.

===== RAM 64K Map Select =====

The lowest 4 paging bits control RAM, bits 4-6 select one of 8 EEPROM pages of 4k each.

The memory decode maps any 32k page of the 512k into $0000-$7FFF.

Writing to it selects different blocks from the 512k to appear in the main map.

E.g. if you write a 1 to EF00 it will duplicate the upper bank in the lower bank.

==== RAM Mapping Note ====

:!: 

Be sure you have RAM switching code in ROM before switching to RAM pages 2 or higher.

ROM code should include functions to:
  * Register-only Block Copy from RAM pages 0 and 1 into pages 2 and higher
    * The block copy must be split in two halves:
    * The first half gets the source byte into a register (only)
    * Switch the RAM page page but let the Program Counter fall through into the next ROM instruction which is the start of the second half of the copy 
    * The second half takes the register and posts it into a destination address of the destination RAM page
    * Then switch BACK to the source RAM page and fall through into the next ROM address which continue copying from source RAM page 
  * Transfer the Program Counter into the destination address of the destination RAM page to start running code from
===== Upper 32K =====

The region from $8000-$DFFF is not affected by the paging register contents.

The logic fixes ROM and I/O in place.

So you can run paging code resident there.

For that reason, it's also recommended to put any ISR's there.

==== Hidden RAM Access ====

When you map page 1 to page 0, only the RAM is relocated.

So, the RAM that is hidden "under" ROM and I/O becomes visible that way.

==== ASSIST09 ====

The ASSIST09 'M' command is read-modify-write (RMW) and the Memory Select Latch is not qualified with read/write.

The CPU can write it but if you try doing it manually with the monitor, it will write garbage into the latch.

===== RTS =====
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