Exile In Paradise

Stranded on Earth...

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sst-6809:memory_map [2024/10/11 16:15] – [56K NVRAM] robertsst-6809:memory_map [2024/10/13 21:30] (current) – add note for ASSIST09 expansion ROM area robert
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 ====== Memory Map ====== ====== Memory Map ======
  
-^ Start - End ^ Purposes ^ +^ Use  ^  Start - End  ^ Implementation  ^ 
-| 0000 - DFFF | [[#56K NVRAM]] | +| RAM |  0000 - DFFF  | [[#56K NVRAM]] | 
-| x000 - x3FF | [[#Main Bus Select 0 1K]] | +| ::: |  D000 - D0FF  | ASSIST09 working RAM, stacks and vector copies | 
-| x400 - x7FF | [[#Main Bus Select 1 1K]] | +| I/O |  E000 - E3FF  | [[#Main Bus Select 0 1K]] | 
-| x800 - xAFF | unassigned | +| ::: |  E400 - E7FF  | [[#Main Bus Select 1 1K]] | 
-| xB00 - xBFF | [[#ACIA Select 256b]] | +| ::: |  E800 - EAFF  | unassigned | 
-| xC00 - xEFF | unassigned | +| ::: |  EB00 - EBFF  | [[#ACIA Select 256b]] | 
-| xF00 - xFFF | [[#Memory Latch Select 256b]] | +| ::: |  EC00 - EEFF  | unassigned | 
-| F000 - FFFF | [[#EEPROM 4K]] |+| ::: |  EF00 - EFFF  | [[#Memory Latch Select 256b]] | 
 +| ROM |  F000 - FFFF  | [[#EEPROM 4K]] | 
 +| ::: |  F000 - F3FF  | [[ASSIST09]] Expansion ROM area (unused) | 
 +| ::: |  F800 - FFFF  | [[ASSIST09]] | 
 +| MPU |  FFF0 - FFF1  | HD6390 Illegal Opcode/Divide By Zero Trap vector (FFD4) | 
 +| ::: |  FFF2 - FFF3  | SWI3 vector (FFD8) | 
 +| ::: |  FFF4 - FFF5  | SWI2 vector (FFDC)| 
 +| ::: |  FFF6 - FFF7  | /FIRQ vector (FFE0) | 
 +| ::: |  FFF8 - FFF9  | /IRQ vector (FFE4) | 
 +| ::: |  FFFA - FFFB  | SWI vector (FFE8) | 
 +| ::: |  FFFC - FFFD  | /NMI vector (FFEC) | 
 +| ::: |  FFFE - FFFF  | /RESET vector (F837) |
  
-x is the J3 select jumper for 8xxx - Exxx address ranges +The 2.0 board is hard wired for "Exxx" selects in the map above.
- +
-The 2.0 board is hard wired "x" = "E" in the map above.+
  
 The subsequent version has jumpers to locate the I/O block The subsequent version has jumpers to locate the I/O block
  
-The memory decode maps any 32k page of the 512k into $0000-$7FFF. +These use J3 select jumper for 8xxx - Exxx address select range
- +
-The region from $8000-$DFFF is not affected by the paging register contents. +
- +
-So you can run paging code resident there. +
- +
-For that reason, it's also recommended to put any ISR's there. +
- +
-The lowest 4 paging bits control RAM, bits 4-6 select one of 8 EEPROM pages of 4k each. +
- +
-Bit 7 controls the "stat" LED+
  
 ===== 56K NVRAM ===== ===== 56K NVRAM =====
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 The lowest 64KB provides the processor's workspace RAM. The lowest 64KB provides the processor's workspace RAM.
  
-There is a Memory Select Latch that allows mapping 32KB banks from the remaining 456KB of static RAM into the lower 32KB address range of the processor workspace ($0000-$7FFF)+There is a Memory Latch Select that allows mapping 32KB banks from the remaining 456KB of static RAM into the lower 32KB address range of the processor workspace ($0000-$7FFF)
  
 The remaining RAM address range $8000-DFFF remains in place allowing a stable place for interrupt service handlers, stacks, bank mapping code and more. The remaining RAM address range $8000-DFFF remains in place allowing a stable place for interrupt service handlers, stacks, bank mapping code and more.
 +
 +ASSIST09 reserves D000-D100, F000-F3FF for its expansion ROM, and F400-FFFF for itself.
 +
 ===== Main Bus Select 0 1K ===== ===== Main Bus Select 0 1K =====
-:!: Coming as I learn more+ 
 +Briefly, they are active low peripheral segment decodes. 
 + 
 +Only one is extended to the M8 bus. 
 + 
 +Basically, it is similar to the expansion board selects on say, an Apple II. 
 + 
 +It is used along with the five lowest address lines, to select devices on peripheral boards. 
 + 
 +So all of the expansion boards are based at the BSEL address it's connected to, and the 32 bytes at that location. 
 + 
 +You can stack multiple boards if those 32 addresses don't conflict. 
 + 
 +For example, you can combine a VIA board with a Game board, provided the Game Board UART is left uninstalled. 
 + 
 +Or, a Mezz board could be on the bus with some device that decodes at $8-$B as there is a gap there.
  
 ===== Main Bus Select 1 1K ===== ===== Main Bus Select 1 1K =====
-:!: Coming as I learn more+ 
 +If you wanted to host identical devices, for example two VIA's, it's where multiple BSEL come in. 
 + 
 +So one VIA would be on BSEL0 and another on BSEL1. 
 + 
 +All the SBC's have one expansion slot, so only one BSEL. 
 + 
 +But a more advanced board (aka motherboard) would have one bus select for each slot. 
 + 
 +So the additional slot would have BSEL1 replacing the BSEL0 on the first one. 
 + 
 +Ken Willmott cooked this up so that most of the decode could be shared amongst the add on boards. 
 + 
 +A good example of this is the VIA board, which has no decode logic on it at all. 
 + 
 +Just a VIA and bypass caps.
  
 ===== ACIA Select 256b ===== ===== ACIA Select 256b =====
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 ===== Memory Latch Select 256b ===== ===== Memory Latch Select 256b =====
 +
 The paging latch. The paging latch.
  
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 E.g. if you write a 1 to EF00 it will duplicate the upper bank in the lower bank. E.g. if you write a 1 to EF00 it will duplicate the upper bank in the lower bank.
 +
 +The memory decode maps any 32k page of the 512k into $0000-$7FFF.
 +
 +The region from $8000-$DFFF is not affected by the paging register contents.
 +
 +So you can run paging code resident there.
 +
 +For that reason, it's also recommended to put any ISR's there.
 +
 +The lowest 4 paging bits control RAM, bits 4-6 select one of 8 EEPROM pages of 4k each.
 +
 +Bit 7 controls the "stat" LED
  
 The M command is RMW and the latch is not qualified with R/W. The M command is RMW and the latch is not qualified with R/W.
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 So, the RAM that is hidden "under" ROM and I/O becomes visible that way. So, the RAM that is hidden "under" ROM and I/O becomes visible that way.
 +
 ===== EEPROM 4K ===== ===== EEPROM 4K =====
  
 The SST-6809 contains a 32KB EEPROM. The SST-6809 contains a 32KB EEPROM.
  
-The Memory Select Latch allows mapping one of eight 4KB sections of the EEPROM into the memory range $F000-$FFFF which includes the MPU interrupt vectors.+The Memory Latch Select allows mapping one of eight 4KB sections of the EEPROM into the memory range $F000-$FFFF which includes the MPU interrupt vectors. 
 + 
 +Make use of the boot ROM select jumper(s). 
 + 
 +The 2.0 can boot from 4 different segments, the 2.1 only 2. 
 + 
 +But the current EEPROM only has ASSIST09 burned into it. 
 + 
 +The "external ROM" is just the unused space in the other half of the 4k boot ROM. 
 +  
 +Ken just never put anything there. 
 + 
 +At some point Ken could burn another boot into an EEPROM. 
 + 
 +The PTM on the Mezz board can support tracing with ASSIST09, but it needs a jumper to put its interrupt on NMI.
  
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