Exile In Paradise

Stranded on Earth...

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sst-6809:memory_map [2024/10/11 16:30] – [Main Bus Select 0 1K] robertsst-6809:memory_map [2025/04/12 11:34] (current) – robert
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 ====== Memory Map ====== ====== Memory Map ======
  
-^ Start - End ^ Purposes ^ +^ Use  ^  Start - End  ^ Implementation  ^ 
-| 0000 - DFFF | [[#56K NVRAM]] | +| RAM |  0000 - DFFF  | [[56K NVRAM]] | 
-| x000 - x3FF | [[#Main Bus Select 0 1K]] | +| ::: |  D000 - D0FF  | ASSIST09 working RAM, stacks and vector copies | 
-| x400 - x7FF | [[#Main Bus Select 1 1K]] | +| I/O |  E000 - E3FF  | [[Main Bus Select 0 1K]] | 
-| x800 - xAFF | unassigned | +| ::: |  E400 - E7FF  | [[Main Bus Select 1 1K]] | 
-| xB00 - xBFF | [[#ACIA Select 256b]] | +| ::: |  E800 - EAFF  | unassigned | 
-| xC00 - xEFF | unassigned | +| ::: |  EB00 - EBFF  | [[ACIA Select 256b]] | 
-| xF00 - xFFF | [[#Memory Latch Select 256b]] | +| ::: |  EC00 - EEFF  | unassigned | 
-| F000 - FFFF | [[#EEPROM 4K]] |+| ::: |  EF00 - EFFF  | [[Memory Latch Select 256b]] | 
 +| ROM |  F000 - FFFF  | [[EEPROM 4K]] | 
 +| ::: |  F000 - F3FF  | [[ASSIST09]] Expansion ROM area (unused) | 
 +| ::: |  F800 - FFFF  | [[ASSIST09]] | 
 +| MPU |  FFF0 - FFF1  | HD6309 Illegal Opcode/Divide By Zero Trap vector (FFD4) | 
 +| ::: |  FFF2 - FFF3  | SWI3 vector (FFD8) | 
 +| ::: |  FFF4 - FFF5  | SWI2 vector (FFDC)| 
 +| ::: |  FFF6 - FFF7  | /FIRQ vector (FFE0) | 
 +| ::: |  FFF8 - FFF9  | /IRQ vector (FFE4) | 
 +| ::: |  FFFA - FFFB  | SWI vector (FFE8) | 
 +| ::: |  FFFC - FFFD  | /NMI vector (FFEC) | 
 +| ::: |  FFFE - FFFF  | /RESET vector (F837) |
  
-x is the J3 select jumper for 8xxx - Exxx address ranges +The 2.0 board is hard wired for "Exxx" selects in the map above.
- +
-The 2.0 board is hard wired "x" = "E" in the map above.+
  
 The subsequent version has jumpers to locate the I/O block The subsequent version has jumpers to locate the I/O block
  
-The memory decode maps any 32k page of the 512k into $0000-$7FFF. +These use J3 select jumper for 8xxx - Exxx address select range
- +
-The region from $8000-$DFFF is not affected by the paging register contents. +
- +
-So you can run paging code resident there. +
- +
-For that reason, it's also recommended to put any ISR's there. +
- +
-The lowest 4 paging bits control RAM, bits 4-6 select one of 8 EEPROM pages of 4k each. +
- +
-Bit 7 controls the "stat" LED +
- +
-===== 56K NVRAM ===== +
- +
-The SST-6809 has 512KB of static RAM. +
- +
-The lowest 64KB provides the processor's workspace RAM. +
- +
-There is a Memory Select Latch that allows mapping 32KB banks from the remaining 456KB of static RAM into the lower 32KB address range of the processor workspace ($0000-$7FFF) +
- +
-The remaining RAM address range $8000-DFFF remains in place allowing a stable place for interrupt service handlers, stacks, bank mapping code and more. +
-===== Main Bus Select 0 1K ===== +
- +
-Briefly, they are active low peripheral segment decodes. +
- +
-Only one is extended to the M8 bus. +
- +
-Basically, it is similar to the expansion board selects on say, an Apple II. +
- +
-It is used along with the five lowest address lines, to select devices on peripheral boards. +
- +
-So all of the expansion boards are based at the BSEL address it's connected to, and the 32 bytes at that location. +
- +
-You can stack multiple boards if those 32 addresses don't conflict. +
- +
-For example, you can combine a VIA board with a Game board, provided the Game Board UART is left uninstalled. +
- +
-Or, a Mezz board could be on the bus with some device that decodes at $8-$B as there is a gap there. +
- +
- +
-===== Main Bus Select 1 1K ===== +
-:!: Coming as I learn more +
- +
-===== ACIA Select 256b ===== +
- +
-The Status, Control, TX, and RX registers of a Motorola MC6850 or Hitachi HD6350 Asynchronous Communication Interface Adapter (ACIA) are mapped into this 256 byte page. +
- +
-The ACIA has 4 registers accessible through 2 memory mapped input/output (MMIO) addresses. +
- +
-A read from $EB00 will return the content of the ACIA Status register. +
- +
-A write to $EB00 will update the ACIA Control register with new configuration. +
- +
-A read from $EB01 will return received byte from the ACIA RX Data register. +
- +
-A write to $EB01 will update the ACIA TX Data register with a new byte to transmit. +
- +
-===== Memory Latch Select 256b ===== +
-The paging latch. +
- +
-Writing to it selects different blocks from the 512k to appear in the main map. +
- +
-E.g. if you write a 1 to EF00 it will duplicate the upper bank in the lower bank. +
- +
-The M command is RMW and the latch is not qualified with R/W. +
- +
-The CPU can write it but if you try doing it manually with the monitor, it will write garbage into the latch. +
- +
-If you store in a $80 it should change the status LED +
- +
-To be more specific, $80 turns the LED off and $00 turns it on as it is a pulldown and should be on at reset. +
- +
-The logic fixes ROM and I/O in place. +
- +
-When you map page 1 to page 0, only the RAM is relocated. +
- +
-So, the RAM that is hidden "under" ROM and I/O becomes visible that way. +
-===== EEPROM 4K ===== +
- +
-The SST-6809 contains a 32KB EEPROM. +
- +
-The Memory Select Latch allows mapping one of eight 4KB sections of the EEPROM into the memory range $F000-$FFFF which includes the MPU interrupt vectors.+
  
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