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Memory Map
| Start - End | Purposes |
|---|---|
| 0000 - DFFF | 56K NVRAM |
| x000 - x3FF | Main Bus Select 0 1K |
| x400 - x7FF | Main Bus Select 1 1K |
| x800 - xAFF | unassigned |
| xB00 - xBFF | ACIA Select 256b |
| xC00 - xEFF | unassigned |
| xF00 - xFFF | Memory Latch Select 256b |
| F000 - FFFF | EEPROM 4K |
x is the J3 select jumper for 8xxx - Exxx address ranges
The 2.0 board is hard wired “x” = “E” in the map above.
The subsequent version has jumpers to locate the I/O block
The memory decode maps any 32k page of the 512k into $0000-$7FFF.
The region from $8000-$DFFF is not affected by the paging register contents.
So you can run paging code resident there.
For that reason, it's also recommended to put any ISR's there.
The lowest 4 paging bits control RAM, bits 4-6 select one of 8 EEPROM pages of 4k each.
Bit 7 controls the “stat” LED
56K NVRAM
Coming as I learn more
Main Bus Select 0 1K
Coming as I learn more
Main Bus Select 1 1K
Coming as I learn more
ACIA Select 256b
Coming as I learn more
Memory Latch Select 256b
The paging latch.
Writing to it selects different blocks from the 512k to appear in the main map.
E.g. if you write a 1 to EF00 it will duplicate the upper bank in the lower bank.
The M command is RMW and the latch is not qualified with R/W.
The CPU can write it but if you try doing it manually with the monitor, it will write garbage into the latch.
If you store in a $80 it should change the status LED
The logic fixes ROM and I/O in place.
When you map page 1 to page 0, only the RAM is relocated.
So, the RAM that is hidden “under” ROM and I/O becomes visible that way.
EEPROM 4K
Coming as I learn more
Return to SST-6809