The paging latch.

Bit 7 controls the “stat” LED

If you store in a $80 it should change the status LED

To be more specific, $80 turns the LED off and $00 turns it on as it is a pulldown and should be on at reset.

Bits 6-4 of the Memory Latch Select switches between 4K ROM banks 0 to 7 of the 32K EEPROM.

The lowest 4 paging bits control RAM, bits 4-6 select one of 8 EEPROM pages of 4k each.

The memory decode maps any 32k page of the 512k into $0000-$7FFF.

Writing to it selects different blocks from the 512k to appear in the main map.

E.g. if you write a 1 to EF00 it will duplicate the upper bank in the lower bank.

The region from $8000-$DFFF is not affected by the paging register contents.

The logic fixes ROM and I/O in place.

So you can run paging code resident there.

For that reason, it's also recommended to put any ISR's there.

When you map page 1 to page 0, only the RAM is relocated.

So, the RAM that is hidden “under” ROM and I/O becomes visible that way.

The M command is RMW and the latch is not qualified with R/W.

The CPU can write it but if you try doing it manually with the monitor, it will write garbage into the latch.

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