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Memory Map
| Use | Start - End | Implementation |
|---|---|---|
| RAM | 0000 - DFFF | 56K NVRAM |
| D000 - D0FF | ASSIST09 working RAM, stacks and vector copies | |
| I/O | E000 - E3FF | Main Bus Select 0 1K |
| E400 - E7FF | Main Bus Select 1 1K | |
| E800 - EAFF | unassigned | |
| EB00 - EBFF | ACIA Select 256b | |
| EC00 - EEFF | unassigned | |
| EF00 - EFFF | Memory Latch Select 256b | |
| ROM | F000 - FFFF | EEPROM 4K |
| F000 - F3FF | ASSIST09 Expansion ROM area (unused) | |
| F800 - FFFF | ASSIST09 | |
| MPU | FFF0 - FFF1 | HD6390 Illegal Opcode/Divide By Zero Trap vector (FFD4) |
| FFF2 - FFF3 | SWI3 vector (FFD8) | |
| FFF4 - FFF5 | SWI2 vector (FFDC) | |
| FFF6 - FFF7 | /FIRQ vector (FFE0) | |
| FFF8 - FFF9 | /IRQ vector (FFE4) | |
| FFFA - FFFB | SWI vector (FFE8) | |
| FFFC - FFFD | /NMI vector (FFEC) | |
| FFFE - FFFF | /RESET vector (F837) |
The 2.0 board is hard wired for “Exxx” selects in the map above.
The subsequent version has jumpers to locate the I/O block
These use J3 select jumper for 8xxx - Exxx address select range
Main Bus Select 1 1K
If you wanted to host identical devices, for example two VIA's, it's where multiple BSEL come in.
So one VIA would be on BSEL0 and another on BSEL1.
All the SBC's have one expansion slot, so only one BSEL.
But a more advanced board (aka motherboard) would have one bus select for each slot.
So the additional slot would have BSEL1 replacing the BSEL0 on the first one.
Ken Willmott cooked this up so that most of the decode could be shared amongst the add on boards.
A good example of this is the VIA board, which has no decode logic on it at all.
Just a VIA and bypass caps.
ACIA Select 256b
The Status, Control, TX, and RX registers of a Motorola MC6850 or Hitachi HD6350 Asynchronous Communication Interface Adapter (ACIA) are mapped into this 256 byte page.
The ACIA has 4 registers accessible through 2 memory mapped input/output (MMIO) addresses.
A read from $EB00 will return the content of the ACIA Status register.
A write to $EB00 will update the ACIA Control register with new configuration.
A read from $EB01 will return received byte from the ACIA RX Data register.
A write to $EB01 will update the ACIA TX Data register with a new byte to transmit.
Memory Latch Select 256b
The paging latch.
Writing to it selects different blocks from the 512k to appear in the main map.
E.g. if you write a 1 to EF00 it will duplicate the upper bank in the lower bank.
The memory decode maps any 32k page of the 512k into $0000-$7FFF.
The region from $8000-$DFFF is not affected by the paging register contents.
So you can run paging code resident there.
For that reason, it's also recommended to put any ISR's there.
The lowest 4 paging bits control RAM, bits 4-6 select one of 8 EEPROM pages of 4k each.
Bit 7 controls the “stat” LED
The M command is RMW and the latch is not qualified with R/W.
The CPU can write it but if you try doing it manually with the monitor, it will write garbage into the latch.
If you store in a $80 it should change the status LED
To be more specific, $80 turns the LED off and $00 turns it on as it is a pulldown and should be on at reset.
The logic fixes ROM and I/O in place.
When you map page 1 to page 0, only the RAM is relocated.
So, the RAM that is hidden “under” ROM and I/O becomes visible that way.
EEPROM 4K
The SST-6809 contains a 32KB EEPROM.
The Memory Latch Select allows mapping one of eight 4KB sections of the EEPROM into the memory range $F000-$FFFF which includes the MPU interrupt vectors.
Make use of the boot ROM select jumper(s).
The 2.0 can boot from 4 different segments, the 2.1 only 2.
But the current EEPROM only has ASSIST09 burned into it.
The “external ROM” is just the unused space in the other half of the 4k boot ROM.
Ken just never put anything there.
At some point Ken could burn another boot into an EEPROM.
The PTM on the Mezz board can support tracing with ASSIST09, but it needs a jumper to put its interrupt on NMI.
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