COMMODORE 64NIC+ PROGRAMMING

ABOUT THIS ARTICLE

FIXME This is a work in progress and is not yet complete.

ABOUT THE 64NIC+

With the power off, install the 64NIC+ into the Commodore's expansion slot, also known as the cartridge slot and connect an Ethernet cable.

64NIC+ interfaces the ISA-bus-compatible Crystal (Cirrus Logic) CS8900A embedded ethernet controller with the C64/C128 bus.

As the CS8900A requires only 16 address locations, support logic allows the base address to reside on any 16 byte boundary in the IO address space.

A toggle switch on the side of the unit selects IO1 or IO2 address range.

To support a normal mapping of the registers into the address space and a “flipped” register setup as used by the RetroReplay RR-NET interface, another switch changes the register configuration.

The remaining 2 switches enable the onboard 32-pin EPROM socket and select whether 64 or 128 mode for the EPROM.

Finally, the 16 position rotary switch allows selection of 16kB banks of data from the EPROM.

Toggle switches are as follows, listed from switch located furthest from cartridge port edge connector:

Switch Function (Up) Function (Down)
1 RR-NET Register Configuration Standard Configuration
2 EPROM socket disabled EPROM socket enabled
3 128 mode for EPROM 64 mode for EPROM
4 IO1 Usage IO2 Usage

~ Excerpted from 64NIC+ Network Card (RetroInnovations)

ABOUT THE CIRRUS CS8900A

The CS8900A is a low-cost network controller for embedded applications.

The CS8900A includes on-chip RAM, 10Base-T transmit-and-receive filters and a direct ISA-Bus interface with 24 mA drivers.

Its unique PacketPage architecture automatically adapts to changing network traffic patterns and available system resources.

~ Excerpted from CS8900A (cirrus)

Three documents from the Cirrus site cover all of the programming information you need for this card:

RR-NET

RR-Net is based on the Cirrus logic CS8900a (Crystal LAN).

The chip is used in 8-bit mode, so the 8 registers of an NE2000 are spread over 16 registers in an 8-bit system.

If you compare [the RR-net] register map[s] to the register map in AN181, you might notice that the first and the second half of the register set is swapped.

This has been done because the accessory connector of the Retro Replay does not provide the full range of registers available on the Amiga clockport.

The first two bytes are control registers of the freezer cartridge, and this swapping moves the unnecessary register-pair (IRQ status queue) into the “invisible” area of the cartridge.

The 8-bit mode of the chip does not support IRQs (see Cirrus logic application note AN181).

Although the Amiga makes the interrupt status queue registers available, it does not have any effect.

Even if you try to activate the chip's IRQ features, it will not have any effect.

The IRQ line of the chip is not wired on RR-Net at all!

When RR-Net is connected to the clockport of a “carrier card”, do not forget to enable the clockport (by setting bit 0 in $de01 on Retro Replay), see MMC64, MMC Replay or Chameleon for more information.

~ Adapted from RR-Net (icomp)

64NIC+ PROGRAMMING INTERFACE

The 64NIC+ toggle switches allow you to choose from Normal or RR-net register mappings, and from the Commodore IO1 or IO2 address mapping ranges.

From a programmer's standpoint, this creates four possible programming configurations for the 64NIC+

RR-Net Register Map in IO1 Address Space

C64 Register Read/Write? Meaning
N/A Read-Only Interrupt Status Queue
$DE02/$DE03 Read/Write PacketPage pointer
$DE04/$DE05 Read/Write PacketPage Data (Port 0)
$DE06/$DE07 Read/Write PacketPage Data (Port 1)
$DE08/$DE09 Read/Write Receive/Transmit Data (Port 0)
$DE0A/$DE0B Read/Write Receive/Transmit Data (Port 1)
$DE0C/$DE0D Write-Only TxCMD (Transmit Command)
$DE0E/$DE0F Write-Only TxLength (Transmit Length)

(all 16bit register pairs appear as little endian, ie the low byte first, then the high byte)

~ Adapted from RR-Net (icomp)

Normal Register Map in IO1 Address Space

Addresses Type Description
$DE00/$DE01 Read/Write Receive/Transmit Data (Port 0)
$DE02/$DE03 Read/Write Receive/Transmit Data (Port 1)
$DE04/$DE05 Write Only TxCMD (Transmit Command)
$DE06/$DE07 Write Only TxLength (Transmit Length)
$DE08/$DE09 Read Only Interrupt Status Queue
$DE0A/$DE0B Read/Write Packet Page Pointer
$DE0C/$DE0D Read/Write Packet Page Data (Port 0)
$DE0E/$DE0F Read/Write Packet Page Data (Port 1)

~ Adapted from Cirrus Application Note 181, page 1

RR-Net Register Map in IO2 Address Space

C64 Register Read/Write? Meaning
N/A Read-Only Interrupt Status Queue
$DF02/$DF03 Read/Write PacketPage pointer
$DF04/$DF05 Read/Write PacketPage Data (Port 0)
$DF06/$DF07 Read/Write PacketPage Data (Port 1)
$DF08/$DF09 Read/Write Receive/Transmit Data (Port 0)
$DF0A/$DF0B Read/Write Receive/Transmit Data (Port 1)
$DF0C/$DF0D Write-Only TxCMD (Transmit Command)
$DF0E/$DF0F Write-Only TxLength (Transmit Length)

(all 16bit register pairs appear as little endian, ie the low byte first, then the high byte)

~ Adapted from RR-Net (icomp)

Normal Register Map in IO2 Address Space

Addresses Type Description
$DF00/$DF01 Read/Write Receive/Transmit Data (Port 0)
$DF02/$DF03 Read/Write Receive/Transmit Data (Port 1)
$DF04/$DF05 Write Only TxCMD (Transmit Command)
$DF06/$DF07 Write Only TxLength (Transmit Length)
$DF08/$DF09 Read Only Interrupt Status Queue
$DF0A/$DF0B Read/Write Packet Page Pointer
$DF0C/$DF0D Read/Write Packet Page Data (Port 0)
$DF0E/$DF0F Read/Write Packet Page Data (Port 1)

~ Adapted from Cirrus Application Note 181, page 1

LAYER 1 PHYSICAL

LAYER 3 NETWORK

LAYER 4 TRANSPORT

LAYER 5 SESSION

LAYER 6 PRESENTATION

LAYER 7 APPLICATION

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